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<title>ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values </title></head>
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<h1>ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 55 /r ANDNPD xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm1 and xmm2/mem.</td></tr>
<tr>
<td>VEX.NDS.128.66.0F 55 /r VANDNPD xmm1, xmm2, xmm3/m128</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm2 and xmm3/mem.</td></tr>
<tr>
<td>VEX.NDS.256.66.0F 55/r VANDNPD ymm1, ymm2, ymm3/m256</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in ymm2 and ymm3/mem.</td></tr>
<tr>
<td>EVEX.NDS.128.66.0F.W1 55 /r VANDNPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1.</td></tr>
<tr>
<td>EVEX.NDS.256.66.0F.W1 55 /r VANDNPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1.</td></tr>
<tr>
<td>EVEX.NDS.512.66.0F.W1 55 /r VANDNPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Return the bitwise logical AND NOT of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs a bitwise logical AND NOT of the two, four or eight packed double-precision floating-point values from the first source operand and the second source operand, and stores the result in the destination operand.</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.</p>
<h2>Operation</h2>
<p><strong>VANDNPD (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask*
              IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] (cid:197) (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]
                    ELSE
                         DEST[i+63:i] (cid:197) (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+63:i] = 0
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VANDNPD (VEX.256 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] (cid:197) (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[191:128] (cid:197) (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]
DEST[255:192] (cid:197) (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]
DEST[MAX_VL-1:256] (cid:197) 0</pre>
<p><strong>VANDNPD (VEX.128 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] (cid:197) (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>ANDNPD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[63:0] (cid:197) (NOT(DEST[63:0])) BITWISE AND SRC[63:0]
DEST[127:64] (cid:197) (NOT(DEST[127:64])) BITWISE AND SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);</p>
<p>VANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);</p>
<p>VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);</p>
<p>VANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);</p>
<p>VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);</p>
<p>VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);</p>
<p>VANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);</p>
<p>VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);</p>
<p>ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instruction, see Exceptions Type 4.</td></tr>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E4.</td></tr></table></body></html>